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mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 1 motorola fast sram advance information 256kb and 512kb burstram ? secondary cache modules for powerpc ? prep/chrp platforms the mpc2104/5/6/7 are designed to provide burstable, high performance l2 cache for the powerpc 60x microprocessor family in conformance with the powerpc reference platform (prep) and the powerpc common hardware reference platform (chrp) specifications. these products utilize synchronous or asynchronous data rams. the mpc2104, mpc2105, and mpc2106 utilize synchronous burstrams. the modules are configured as 32k x 72, 64k x 72, and 128k x 72 bits in a 182 (91 x 2) pin dimm format. the mpc2104 uses four of motorola's 5 v 32k x 18; the mpc2105 uses four of the 5 v 64k x 18; the mpc2106 uses eight of the 5 v 64k x 18. for tag bits, a 5 v cache tag ram c onfigured as 16k x 12 for tag field plus 16k x 2 for valid and dirty status bits is used. bursts can be initiated with the ads signal. subsequent burst addresses are generated internal to the burstram by the cnten signal. write cycles are internally self timed and are initiated by the rising edge of the clock (clkx) inputs. eight write enables are provided for byte write control. the mpc2107 utilizes asynchronous data rams. the module is configured as 32k x 64 in the same 182 pin dimm format. again, 5 v cache tag rams configured as 16k x 12 for tag field plus 16k x 2 for valid and dirty status bits are used. burst capability is provided in that two burst addresses bypass the address latch. presence detect pins are available for auto configuration of the cache con- trol. a serial eeprom is optional to provide more indepth description of the cache module. this eeprom will be available on future revisions of the module family. the module family pinout will support 5 v and 3.3 v components for a clear path to lower voltage and power savings. both power supplies must be connected. all of these cache modules are plug and pin compatible with each other. ? powerpcstyle burst counter on chip (mpc2104/5/6) ? flowthrough data i/o (mpc2104/5/6) ? plug and pin compatibility of entire module family ? multiple clock pins for reduced loading ? all cache data and tag i/os are lvttl (3.3 v) compatible (mpc2104/5/6) ? three state outputs ? byte write capability ? fast module clock rates: up to 66 mhz ? fast sram access times: 10 ns for tag ram match 9 ns for data ram (mpc2104/5/6) 15 ns for data ram (mpc2107) ? decoupling capacitors for each fast static ram ? high quality multilayer fr4 pwb with separate power and ground planes ? 182 pin card edge module ? burndy connector, part number: elf182jsc3z50 burstram is a trademark of motorola. powerpc is a trademark of international business machines corp. this document contains information on a new product. specifications and information herein are subject to change without notice. order this document by mpc2104/d semiconductor technical data mpc2104 mpc2105 mpc2106 mpc2107 11/8/95 ? motorola, inc. 1995
pin assignment 182lead dimm top view case tbd v ss pd1/idsdata pd3 dh31 dh29 dh27 dh25 v cc 3 cwe3 dh23 dh21 dh18 v ss dh16 cwe2 dh14 dh13 v cc 5 dh10 dh8 cwe1 dh6 v cc 3 dh4 v ss clk0 v ss dh1 cwe0 dl31 dl30 v ss dl29 dl27 dl25 v cc 5 cwe7 dl23 dl21 dl19 v ss dl17 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 v ss pd0/idsclk pd2 dh30 dh28 dh26 dh24 v cc 3 dp3 dh22 dh20 dh19 v ss dh17 dp2 dh15 dh12 v cc 5 dh11 dh9 dp1 dh7 v cc 3 dh5 dh3 dh2 dh0 dp0 v ss clk1 vss dl28 dl26 dl24 dp7 v cc 5 dl22 dl20 dl18 dl16 v ss dp6 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 cwe6 dl15 dl13 v ss dl10 dl8 cwe5 dl6 v cc 3 dl5 dl2 v ss clk3 v ss clk4 v ss cwe4 ale v cc 3 addr1 reserved cnten0 cnten1 v cc 5 v cc 5 a27 a24 a22 a20 v ss a18 a16 a15 a14 v cc 3 a10 a8 a6 v ss a4 a2 a1 burstmode v cc 5 validin twe standby dirtyout v ss dl14 dl12 dl11 v ss dl9 dp5 dl7 dl4 v cc 3 dl3 dl1 dl0 v ss clk2 v ss dp4 coe0 coe1 v cc 3 addr0 reserved ads0 ads1 v cc 5 v cc 5 a28 a26 a25 a23 v ss a21 a19 a17 a13 v cc 3 a12 a11 a9 v ss a7 a5 a3 a0 v cc 5 tclr match toe dirtyin v ss notes: 1. v cc 5 and v cc 3 must be connected on all modules. mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 2 motorola fast sram
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 3 motorola fast sram mpc2104/mpc2105 block diagram mcm67mx18 a15 k g e dq0 dq8 a13 standby tsc coe0 tsp a14 a26 v cc 5 via 100 w a2 a14 a14 a26 lw baa ads0 cwe0 a2 a12 a1 tclr twe clk2 match dirtyout validin dirtyin toe tag: 16k x 12 + v + d a13 reset a0 a12 tag , tad , e2 sfunc, sg tdq0 tdq10 tdq11 sw tw k match dirtyq validd dirtyd tg clk3 = nc clk4 = nc ale = nc ads1 = nc cnten1 = nc coe1 = nc addr0 = nc addr1 = nc pd2 = nc pd3 j0 x24c00 (optional) scl sda pd0/idsclk pd1/idsdata j2 j3 dq9 dq17 uw clk0 dh0 dh7 + dp0 dh8 dh15 + dp1 cwe1 cnten0 a1 a27 a0 a28 mcm67mx18 a15 k g e dq0 dq8 tsc tsp a2 a14 lw baa cwe2 dq9 dq17 uw clk0 dh16 dh23 + dp2 dh24 dh31 + dp3 cwe3 a1 a0 mcm67mx18 a15 k g e dq0 dq8 tsc tsp a2 a14 lw baa cwe4 dq9 dq17 uw clk1 dl0 dl7 + dp4 dl8 dl15 + dp5 cwe5 a1 a0 mcm67mx18 a15 k g e dq0 dq8 tsc tsp a2 a14 lw baa cwe6 dq9 dq17 uw clk1 dl16 dl23 + dp6 dl24 dl31 + dp7 cwe7 a1 a0 '244 tt1, wtd, e1 tah, pwrdn j5 v ss v cc 5 via 100 w wtq validq v ccq v cc 3 nc 256kb 512kb eeprom eeprom 256kb 512kb j5 no stuff 0 w no stuff 0 w j4 0 w 0 w no stuff no stuff j3 0 w 0 w no stuff no stuff j2 0 w no stuff no stuff no stuff j1 0 w no stuff 0 w no stuff j0 no stuff 0 w no stuff 0 w j4 j1 note: mpc2104 utilizes 32k x 18 burstrams. mpc2105 utilizes 64k x 18 burstrams. nc
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 4 motorola fast sram mpc2106 block diagram 64k x 18 burst k g e dq0 dq8 standby tsc coe0 a13 a26 a0 a15 a13 a28 lw baa ads0 cwe0 a0 a11 tclr twe clk2 match dirtyout validin dirtyin toe tag: 16k x 12 + v + d a0 a13 reset tah, tag , tad sfunc, sg tdq0 tdq11 sw tw k match dirtyq validd dirtyd tg ale = nc addr0 = nc addr1 = nc pd2 = nc pd3 x24c00 (optional) scl sda pd0/idsclk pd1/idsdata j0 dq9 dq17 uw clk0 dh0 dh7 + dp0 dh8 dh15 + dp1 cwe1 cnten0 64k x 18 burst k g e dq0 dq8 tsc a0 a15 lw baa cwe2 dq9 dq17 uw clk1 dh16 dh23 + dp2 dh24 dh31 + dp3 cwe3 64k x 18 burst k g e dq0 dq8 tsc a0 a15 lw baa cwe4 dq9 dq17 uw clk3 dl0 dl7 + dp4 dl8 dl15 + dp5 cwe5 64k x 18 burst k g e dq0 dq8 tsc a0 a15 lw baa cwe6 dq9 dq17 uw clk4 dl16 dl23 + dp6 dl24 dl31 + dp7 cwe7 '244 tt1, wtd pwrdn v ss v cc 5 via 100 w wtq ta , validq v ccq v cc 3 nc 1m eeprom 1m j1 0 w no stuff j0 0 w no stuff a12 64k x 18 burst k g e dq0 dq8 tsc a0 a15 lw baa cwe0 dq9 dq17 uw clk0 dh0 dh7 + dp0 dh8 dh15 + dp1 cwe1 64k x 18 burst k g e dq0 dq8 tsc a0 a15 lw baa cwe2 dq9 dq17 uw clk1 dh16 dh23 + dp2 dh24 dh31 + dp3 cwe3 64k x 18 burst k g e dq0 dq8 tsc a0 a15 lw baa cwe4 dq9 dq17 uw clk3 dl0 dl7 + dp4 dl8 dl15 + dp5 cwe5 64k x 18 burst k g e dq0 dq8 tsc a0 a15 lw baa cwe6 dq9 dq17 uw clk4 dl16 dl23 + dp6 dl24 dl31 + dp7 cwe7 coe1 ads1 cnten1 e2 e1 a12 v dd a13 a26 a0 a11 tclr twe clk2 match dirtyout validin dirtyin toe tag: 16k x 12 + v + d a0 a13 reset tah, tag , tad sfunc, sg tdq0 tdq11 sw tw k match dirtyq validd dirtyd tg tt1, wtd pwrdn v ss v cc 5 via 100 w wtq ta , validq v ccq v cc 3 nc e2 e1 v ss a12 note: all 64k x 18 tsp signals are tied to v cc via a 100 w resistor. edge connector a28 connects to the 64k x 18 a0; edge connector a27 connects to the 64k x 18 a1. j1 14 pal pa12 pa12l nc nc
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 5 motorola fast sram mpc2107 block diagram mcm6206 g e standby a0 coe0 a14 a26 a2 a14 a14 a26 w a1 addr0 cwe0 a2 a13 tclr twe clk2 match dirtyout validin dirtyin toe tag: 16k x 12 + v + d a0 a12 reset tah, tag , tad sfunc, sg tdq0 tdq11 sw tw k match dirtyq validd dirtyd tg clk0, 1, 3, 4 = nc ads0 , ads1 = nc cnten0 , cnten1 = nc a27, a28 = nc dp0 dp7 = nc burstmode = nc pd2 pd3 = nc x24c00 (optional) scl sda pd0/idsclk pd1/idsdata j2 dq0 dq7 dh0 dh7 addr1 mcm6206 mcm6206 mcm6206 '373 tt1, wtd, e1 e2, pwrdn v ss v cc 5 via 100 w wtq ta , validq v ccq v cc 3 nc 256kb eeprom 256kb j3 0 w no stuff j2 0 w no stuff j1 0 w no stuff mcm6206 mcm6206 mcm6206 mcm6206 13 ale g e a0 a2 a14 w a1 cwe1 dq0 dq7 dh8 dh15 g e a0 a2 a14 w a1 cwe2 dq0 dq7 dh16 dh23 g e a0 a2 a14 w a1 cwe3 dq0 dq7 dh24 dh31 g e a0 a2 a14 w a1 cwe4 dq0 dq7 dl0 dl7 coe1 g e a0 a2 a14 w a1 cwe5 dq0 dq7 dl8 dl15 g e a0 a2 a14 w a1 cwe6 dq0 dq7 dl16 dl23 g e a0 a2 a14 w a1 cwe7 dq0 dq7 dl24 dl31 j3 v ss a13 j1 nc
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 6 motorola fast sram pin descriptions pin locations symbol type description 68, 69, 70, 71, 73, 74, 75, 76, 78, 79, 80, 82, 83, 84, 85, 159, 160, 161, 162, 164, 165, 166, 167, 169, 170, 171, 173, 174, 175 a0 a28 input address inputs (msb:0, lsb:28) 62 addr0 input least significant address bit when asynchronous data rams are used. 153 addr1 input next to least significant address bit when asynchronous data rams are used. 30, 56, 117, 146, 148 clk0 clk4 input clock inputs clk2 is for tag ram, clk0, 1, 3, and 4 are for data rams only. for mpc2106 use all the clocks. for mpc2104 or mpc2105 use clk0clk2 only. for mpc2107 use clk2 only. 4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26, 27, 95, 96, 97, 98, 101, 102, 103, 105, 107, 108, 110, 111, 113, 115, 119 dh0 dh31 i/o high data bus (msb:0, lsb:31) 32, 33, 34, 37, 38, 39, 40, 43, 44, 45, 47, 49, 50, 52, 53, 54, 121, 122, 124, 125, 126, 129, 130, 131, 133, 135, 136, 138, 139, 141, 143, 144 dl0 dl31 i/o low data bus (msb:0, lsb:31) 9, 15, 21, 28, 35, 42, 48, 58 dp0 dp7 i/o data parity bits (msb:0, lsb:7) 3, 94 pd2, pd3 output presence detect bits. 2 pd0/idsclk input presence detect bit 0/eeprom serial clock. (eeprom option only.) 93 pd1/idsdata i/o presence detect bit 1/eeprom serial data. (eeprom option only.) 64, 65 ads0 , ads1 input data ram address strobe for mpc2104 or mpc2105 use ads0 only. for mpc2106 use ads0 , ads1 . 151 ale input data ram address latch enable use for asynchronous data ram only. 155, 156 cnten0 , cnten1 input data ram count enables for mpc2104 or mpc2105 use cnten0 only. for mpc2106 use cnten0 , cnten1 . 59, 60 coe0 , coe1 input data ram output enables for mpc2104 or mpc2105 use coe0 only. for all others use coe0 , coe1 . 100, 106, 112, 120, 128, 134, 140, 150 cwe0 cwe7 input data ram write enables (msb:0, lsb:7) 87 tclr input tag ram clear. 88 match output tag ram active high match indication. 178 validin input tag ram valid bit. 179 twe input tag ram write enable. 89 toe input tag ram output enable. 90 dirtyin input dirty input bit. 181 dirtyout output dirty output bit. 180 standby input standby pin. reduces standby power consumption. 176, 63, 154 reserved reserved pin. 8, 23, 51, 61, 77, 99, 114, 142, 152, 168 v cc 3 input + 3.3 v power supply. must be connected. 18, 36, 66, 67, 86, 109, 127, 157, 158, 177 v cc 5 input + 5 v power supply. must be connected. 1, 13, 29, 31, 41, 46, 55, 57, 72, 81, 91, 92, 104, 116, 118, 123, 132, 137, 145, 147, 149, 163, 172, 182 v ss input ground 176 burstmode input burstmode. 0 = linear, 1 = interleaved.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 7 motorola fast sram data ram mcm67m518, mcm67m618 synchronous truth table (see notes 1, 2, and 3) standby ads0 cnten0 cwex clkx address used operation h l x x lh n/a deselected l l x l lh external address write cycle, begin burst l l x h lh external address read cycle, begin burst x h l l lh next address write cycle, continue burst x h l h lh next address read cycle, continue burst x h h l lh current address write cycle, suspend burst x h h h lh current address read cycle, suspend burst notes: 1. x means don't care. 2. all inputs except coe must meet setup and hold times for the lowtohigh transition of clock (clk0 clk4). 3. wait states are inserted by suspending burst. asynchronous truth table (see notes 1 and 2) operation coe i/o status read l data out (dq0 dq8) read h highz write x highz e data in deselected x highz notes: 1. x means don't care. 2. for a write operation following a read operation, coe must be high before the input data required setup time and held high through the input data hold time. data ram mcm6206 asynchronous truth table (see notes 1 and 2) standby coe0 , coe1 cwe0 cwe7 operation i/o status h x x deselected highz l h h output disabled highz l l h read data out l x l write highz notes: 1. x means don't care. 2. for a write operation following a read operation, coe0 , and coe1 must be high before the input data required setup time, and held high through the input data hold time. absolute maximum ratings (voltages referenced to v ss = 0 v) rating symbol value unit power supply voltage v cc 0.5 to + 7.0 v voltage relative to v ss v in , v out 0.5 to v cc + 0.5 v output current (per i/o) data ram ta g i out 30 20 ma power dissipation p d 8.1 w temperature under bias t bias 10 to + 85 c operating temperature t a 0 to +70 c storage temperature t stg 55 to + 125 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. this device contains circuitry that will ensure the output devices are in highz at power up.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 8 motorola fast sram dc operating conditions and characteristics (v cc = 5.0 v 5%, t a = 0 to + 70 c, unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min max unit supply voltage (operating voltage range) v cc 4.75 5.25 v input high voltage v ih 2.2 v cc + 0.3** v input low voltage v il 0.5* 0.8 v *v il (min) = 0.5 v dc; v il (min) = 2.0 v ac (pulse width 20 ns) for i 20.0 ma. ** v ih (max) = v cc + 0.3 v dc; v ih (max) = v cc + 2.0 v ac (pulse width 20 ns) for i 20.0 ma. dc characteristics parameter symbol min max unit input leakage current (all inputs, v in = 0 to v cc ) data ram ta g i lkg(i) e 1.0 5.0 m a output leakage current (coe = v ih , v out = 0 to v cc ) data ram ta g i lkg(o) e 1.0 5.0 m a ttl output low voltage (i ol = + 8.0 ma) v ol e 0.4 v ttl output high voltage (i oh = 4.0 ma) v oh 2.4 e v power supply currents parameter symbol max unit ac supply current (coe = v ih , e = v il , i out = 0 ma, all inputs = v il and v ih , v il = 0.0 v and v ih 3.0 v, cycle time 20 ns) mpc2104 mpc2105 mpc2106 mpc2107 i cca 1480 1420 2840 1400 ma ac standby current (e = v ih , i out = 0 ma, all inputs = v il or v ih , v il = 0.0 v and v ih 3.0 v, cycle time 20 ns) mpc2104 mpc2105 mpc2106 mpc2107 i sb1 620 700 1400 960 ma capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 25 c, periodically sampled rather than 100% tested) parameter symbol typ max unit input capacitance (a13 a28) (data ram control pins) (clk0 clk4) (tag control pins) c in e 16 8 e 15 20 10 5 pf tag output capacitance (match, dirtyout) c out e 7 pf data ram input/output capacitance (dh0 dh31, dl0 dl31) c i/o 6 8 pf tag input/output capacitance (a0 a11) c i/o e 7 pf
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 9 motorola fast sram data rams ac operating conditions and characteristics (v cc = 5.0 v 5% t a = 0 to + 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 1a unless otherwise noted . . . . . . . . . . . . synchronous data rams read/write cycle timing (see notes 1, 2, 3, and 7) mpc2104 mpc2105 mpc2106 parameter symbol min max unit notes cycle time t khkh 15 e ns clock access time t khqv e 9 ns 4 output enable to output valid t glqv e 5 ns clock high to output active t khqx1 6 e ns clock high to output change t khqx2 3 e ns output enable to output active t glqx 0 e ns output disable to q highz t ghqz 2 6 ns clock high to q highz t khqz e 6 ns clock high pulse width t khkl 5 e ns clock low pulse width t klkh 5 e ns setup time address t avkh 7.5 e ns 5, 6 setup times: address status data in write address advance chip enable t svkh t dvkh t wvkh t bavvkh t evkh 2.5 e ns 5 hold times: address address status data in write address advance chip enable t khax t khtsx t khdx t khwx t khbax t khex 0.5 e ns 5 notes: 1. in setup and hold times, w (write) refers to either one or both byte write enables lw and uw . 2. all read and write cycle timings are referenced from clk or coe . 3. coe is a don't care when uw or lw is sampled low. 4. maximum access times are guaranteed for all possible powerpc external bus cycles. 5. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk whenever tsp or tsc is low, and the chip is selected. all other synchronous inputs must meet the specified setup and hold times for all rising edges of clk when the chip is enabled. chip enable must be valid at each rising edge of clock for the device (when tsp or tsc is low) to remain enabled. 6. 5 ns of setup delay is incurred in address buffers. 7. applies to mpc2104, mpc2105, and mpc2106.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 10 motorola fast sram synchronous data ram read cycle clk1, clk0 ads0 a(12, 13, 14 26) (see note 1) cwe0 cwe7 standby cnten0 coe data out read burst read t khkh t khkl t klkh a1 a2 t avkh t khax t khqx1 t ghqz t khqv t khqz q (a1) q (a2) q (a2 + 1) q (a2 + 2) t tsvkh t khtsx t wvkh t khwx t evkh t khex t bavkh t khbax t khqv t glqv t glqx t khqx2 notes: 1. cache addresses used are: 14 26 for mpc2104 and mpc2107; 13 26 for mpc2105; and 12 26 for mpc2106. 2. q1 (a2) represents the first ouput from the external address a2; q2 (a2) represents the next output data in the burst sequence with a2 as the base address. q (a2 + 3)
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 11 motorola fast sram synchronous data ram write cycle clk1, clk0 ads0 a(12, 13, 14 26) cwe0 cwe7 standby cnten0 data in single write burst write t khkh t khkl t klkh a1 a2 t avkh t khax d (a1) d (a2) d (a2 + 1) d (a2 + 2) t wvkh t khwx t evkh t khex t bavkh t khbax notes: 1. cache addresses used are: 14 26 for mpc2104 and mpc2107; 13 26 for mpc2105; and 12 26 for mpc2106. 2. coe0 = v ih t svkh t khtsx t avkh t khax d (a2 + 3) t dvkh t khdx
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 12 motorola fast sram ac operating conditions and characteristics (v cc = 5.0 v 5% t a = 0 to + 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 1a unless otherwise noted . . . . . . . . . . . . asynchronous data rams read cycle timing (see notes 1 and 8) mpc210715 parameter symbol min max unit notes cycle time t avav 15 e ns 2 address access time t avqv e 15 ns enable access time t elqv e 15 ns 3 output enable access time t glqv e 8 ns output hold from address change t axqx 4 e ns 4, 5, 6 enable low to output active t elqx 4 e ns 4, 5, 6 enable high to output highz t ehqz 0 8 ns 4, 5, 6 output enable low to output active t glqx 0 e ns 4, 5, 6 output enable high to output highz t ghqz 0 7 ns 4, 5, 6 power up time t elicch 0 e ns power down time t ehiccl e 15 ns notes: 1. w is high for read cycle. 2. all timings are referenced from the last valid address to the first transitioning address. 3. addresses valid prior to or coincident with e going low. 4. at any given voltage and temperature, t ehqz (max) is less than t elqx (min), and t ghqz (max) is less than t glqx (min), both for a given device and from device to device. 5. transition is measured 500 mv from steadystate voltage with load of figure 1b. 6. this parameter is sampled and not 100% tested. 7. device is continuously selected (e = v il , coe0 = v il ). 8. applies to mpc2107.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 13 motorola fast sram asynchronous read cycle 1 (see note 7) q (data out) a (address) data valid previous data valid t avav t axqx t avqv asynchronous read cycle 2 (see note 3) t ehqz data valid t ghqz t avav t elqx t elqv e (chip enable) q (data out) a (address) t avqv t glqx t glqv g (output enable) v cc supply current t ehiccl t elicch highz highz
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 14 motorola fast sram asynchronous data rams write cycle 1 (see notes 1 and 2) mpc210715 parameter symbol min max unit notes write cycle time t avav 15 e ns 3 address setup time t avwl 0 e ns address valid to end of write t avwh 12 e ns write pulse width t wlwh t wleh 12 e ns write pulse width, g high t wlwh t wleh 10 e ns 4 data valid to end of write t dvwh 7 e ns data hold time t whdx 0 e ns write low to output highz t wlqz 0 7 ns 5,6,7 write high to output active t whqx 5 e ns 5,6,7 write recovery time t whax 0 e ns notes: 1. a write occurs during the overlap of e low and w low. 2. if e goes low coincident with or after w goes low, the output will remain in a high impedance state. 3. all timings are referenced from the last valid address to the first transitioning address. 4. if e v ih , the output will remain in a high impedance state. 5. at any given voltage and temperature, t wlqz (max) is less than t whqx (min), both for a given device and from device to device. 6. transition is measured 500 mv from steadystate voltage with load of figure 1b. 7. this parameter is sampled and not 100% tested. asynchronous write cycle 1 (w controlled, see notes 1 and 2) data valid t dvwh t avwl t avwh t avav t whax t wlwh t whdx t wlqz t whqx highz highz a (address) w (write enable) e (chip enable) q (data out) d (data in) t wleh
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 15 motorola fast sram asynchronous data rams write cycle 2 (e controlled, see notes 1 and 2) mpc210715 parameter symbol min max unit notes write cycle time t avav 15 e ns 0 address setup time t avel 0 e ns address valid to end of write t aveh 12 e ns enable to end of write t eleh t elwh 10 e ns 3, 4 data valid to end of write t dveh 7 e ns data hold time t ehdx 0 e ns write recovery time t ehax 0 e ns notes: 1. a write occurs during the overlap of e low and w low. 2. all timings are referenced from the last valid address to the first transitioning address. 3. if e goes low coincident with or after w goes low, the output will remain in a high impedance state. 4. if e goes high coincident with or before w goes high, the output will remain in a high impedance state. asynchronous write cycle 2 (e controlled, see note 1) t ehdx t dveh t ehax t elwh t eleh t avel t aveh data valid t avav highz a (address) w (write enable) e (chip enable) q (data out) d (data in) t wleh
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 16 motorola fast sram tag ram reset function truth table (see notes 1 and 2) tclr clk twe tag vld out dty out wt out match ta operation power l l h h highz l (3) l (3) l (3) l (3) highz reset status active l l h l e e e e e e not allowed e notes: 1. h = v ih , l = v il , x = don`t care, e = unrelated. 2. toe is x for this table. read function truth table (see notes 1, 2, and 3) toe twe clk tag vld in dty in wt in vld out dty out wt out match operation l h x d out e e e e e e d out read tag i/o h x x highz e e e e e e e tag i/o disable write function truth table (see notes 1 and 2) toe twe clk tag vld in dty in wt in vld out dty out wt out match operation h l l h d in e e e d out d out d out l write tag i/o l l l h e e e e e e e e not allowed notes: 1. h = v ih , l = v il , x = don`t care, e = unrelated. 2. this table applies when reset and pwrdn are high. 3. d out in this case is the same as d in . the input data is written through to the outputs during the write operation. match function truth table (see notes 1 through 4) toe twe tag vld (4) dty (4) wt (4) match operation x x e e e e d out selected l h d out e e e l read tag i/o h l d in d in d in d in l write tag i/o, status bits h h tag in l e e l invalid data dedicated status bits h h tag in h e e m match dedicated status bits notes: 1. h = v ih , l = v il , x = don`t care, e = unrelated. 2. m = high if tag in equals the memory contents at the address; m = low if tag in does not equal the ocntents at that address. 3. pwrdn and reset are high for this table. oes and clk are x. 4. this column represents the stored memory cell data for the given status bit at the selected address.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 17 motorola fast sram tag ram ac operating conditions and characteristics (v cc = 5.0 v 5%, t a = 0 to + 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing measurement reference level 1.5 v . . . . . . . . . . . . . output load figure 1a unless otherwise noted . . . . . . . . . . . . . . . . tag ram read cycle (see notes 1 through 4) tag ram parameter symbol min max unit notes clock access time t khqv e 10 ns output enable to output valid t glqv e 8 ns output enable to output active t glqx 0 e ns output disable to q highz t ghqz 1 6 ns status bit hold from address change t axsx 3 e ns address access time status bits t avsv e 10 ns tag bit hold from address change t avqx 3 e ns address access time tag bits t avqv e 12 ns notes: 1. setup and hold times, w (write) referes to twe . 2. a read cycle is defined by twe high. a write cycle is defined by twe low. 3. maximum access times are guaranteed for all possible mc68040 and powerpc external bus cycles. 4. tag reads are asynchronous. tag ram write cycle (see notes 1 through 4) tag ram parameter symbol min max unit notes cycle time t khkh 15 e ns clock high pulse width t khkl 4.5 e ns clock low pulse width t klkh 4.5 e ns clock high to output active t khqx 1.5 e ns setup times address write t avkh t wvkh 3 e ns hold times address write t khax t khwx 1.5 e ns status output hold t khsx 0 e ns clock high to status bits valid t khsv e 9 ns notes: 1. setup and hold times, w (write) referes to twe . 2. a read cycle is defined by twe high. a write cycle is defined by twe low. 3. maximum access times are guaranteed for all possible mc68040 and powerpc external bus cycles. 4. tag writes are synchronous.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 18 motorola fast sram tag ram write and read cycles clk a(12, 13, twe a0 a11 toe valid valid valid valid input valid output valid output valid output valid valid valid valid valid t avkh t khax status write tag read tag write after read t wvkh t khwx t wvkh t khwx t khsv t khsx t wvkh t khwx t khqv t khqx t avsv t ghqz t glqx t axsx validin dirtyin dirtyout t khkl t klkh t khkh t glqv (see note 2) 1426) (see note 3) t avqv t axqx t avkh t khax (see note 1) (see note 1) t avsv t axsx note: 1. transition is measured plus or minus 200 mv from steady state. 2. tclr = high. tag read after write 3. cache addresses used are: 1426 for mpc2004 and mpc2007; 1326 for mpc2005; 1226 for mpc2006 and mpc2009.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 19 motorola fast sram tag ram match cycle tag ram parameter symbol min max unit notes clock high write to match invalid t khml e 7 ns clock high read to match valid t khmv e 10 ns address valid to match valid t avmv e 10 ns match valid hold from address change t axmx 2 e ns toe low to match invalid t glml e 7 ns toe high to match valid t ghmx e 8 ns tag ram reset (tclr ) cycle tag ram parameter symbol min max unit notes tclr setup time t stc 4 e ns tclr hold time t htc 1 e ns status bit reset time t srst e 60 ns status bit hold from tclr low t shrs 2 e ns tclr low to match invalid t rsml e 10 ns tclr high to match valid t rsmv e 100 ns tclr low to tag highz t rsqz e 10 ns tclr high to tag active t rsqx e 100 ns standby setup to tclr low t pdsr 30 e ns tclr high to twe low t rhwx 80 e ns ac test loads output z 0 = 50 w 50 w v l = 1.5 v figure 1a figure 1b 5 pf +5 v output 255 w 480 w timing limits the table of timing values shows either a minimum or a maximum limit for each param- eter. input requirements are specified from the external system point of view. thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). on the other hand, responses from the memory are specified from the device point of view. thus, the access time is shown as a maximum since the device never pro- vides data later than that time.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 20 motorola fast sram match clk a(12, 13, tag ram match cycle valid match valid valid t avmv t axmx t khwx t khwx t wvkh t wvkh t wvkh twe a0 a11 toe valid address valid match data from: processor processor tag ram valid (1426)* t glml t glmx t khml t khmv * cache addresses used are: 1426 for mpc2004 and mpc2007; 1326 for mpc2005; 1226 for mpc2006.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 21 motorola fast sram match clk t htc tag ram tclr function * transition is measured plus or minus 200 mv from steady state. t rsqx t srst t stc t wvkh t rsqz* t rhwx a0 a11 twe dirtyout tclr valid t shrs t rsmv
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 22 motorola fast sram ordering information (order by full part number) mpc 210x xx xx motorola memory prefix part number full part numbers e mpc2104sg66 mpc2105sg66 mpc2106sg66 mpc2107sg15 speed (66 = 66 mhz, synchronous) package (sg = gold pad simm) (15 = 15 ns asynchronous) mpc2104 = 256kb, synchronous mpc2105 = 512kb, synchronous mpc2106 = 1mb, synchronous mpc2107 = 256kb, asynchronous motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters can and do vary in different applications. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 23 motorola fast sram
mpc2104 ? mpc2105 ? mpc2106 ? mpc2107 24 motorola fast sram how to reach us: usa / europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmfax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mpc2104/d
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